There exists a continuing need to improve the feature size (i.e., smallest line width), speed and power consumption of semiconductor devices such as processors and DRAM storage.
The embodiments of the invention relate to a new type of memory cell, based on a floating body cell architecture and implemented using a quantum well FET for ultra low power application. The usage of a quantum well PET in a floating body architecture offers improved size, speed and power consumption compared to conventional DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory).